About our client :
US based company specialized in Semiconductor -Wireless ,Networking & ,Embedded Products.
Requirement
Experience : 3 -5 Years
Location : Bangalore
Qualification : BE/BTECH.ME/MTECH/MCA/MSc
Position : Layout Designer
Job Code : Standard Cells/Memories
Job Description:
Profile Description:
· To design and develop layouts for
1. Standard cells for basic cells to complex cells
2. SRAM compiler and full custom memories (macro/ block/leaf cells)
· Should have understanding of standard cell architecture, layout challenges in high density and performance libraries.
· Should have understanding of different memory architectures
· Experience and familiarity in various physical verification checks – DRC, LVS, ERC, EM, etc.
· Should have understanding and working knowledge of good layout practices for lower process nodes 22nm, 28nm and 45nm.
· Good understanding of deep sub-micron and DFM issues in layout design.
· Thorough working knowledge of layout design and physical verification tools - Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
· Responsible for timely and quality execution of layout design
Preferable to have good knowledge of scripting languages – Perl, skill and shell etc
Interested Professionals mail your resumes to swapna.mohan@roljobs.com .
If you would like to discuss an opportunity, please call me at (080) 4282-1605.
US based company specialized in Semiconductor -Wireless ,Networking & ,Embedded Products.
Requirement
Experience : 3 -5 Years
Location : Bangalore
Qualification : BE/BTECH.ME/MTECH/MCA/MSc
Position : Layout Designer
Job Code : Standard Cells/Memories
Job Description:
Profile Description:
· To design and develop layouts for
1. Standard cells for basic cells to complex cells
2. SRAM compiler and full custom memories (macro/ block/leaf cells)
· Should have understanding of standard cell architecture, layout challenges in high density and performance libraries.
· Should have understanding of different memory architectures
· Experience and familiarity in various physical verification checks – DRC, LVS, ERC, EM, etc.
· Should have understanding and working knowledge of good layout practices for lower process nodes 22nm, 28nm and 45nm.
· Good understanding of deep sub-micron and DFM issues in layout design.
· Thorough working knowledge of layout design and physical verification tools - Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
· Responsible for timely and quality execution of layout design
Preferable to have good knowledge of scripting languages – Perl, skill and shell etc
Interested Professionals mail your resumes to swapna.mohan@roljobs.com .
If you would like to discuss an opportunity, please call me at (080) 4282-1605.
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