Showing posts with label ASIC or FPGA Design. Show all posts
Showing posts with label ASIC or FPGA Design. Show all posts

Monday, April 16, 2012

RTL Engineering Professionals

RTL Design Professionals

Mandatory Skills:

1) USB 2.0 / 3.0
2) ASIC or FPGA Design



3) RTL Coding using Verilog / VHDL


4) Microarchitecture Definition


5) DDR/AMBA/AHB/APB/AXI / PCIe


Minimum - 5 to 15 Years of experience
Location - Chennai


Regards,
Priyanka Srivastava,
Tel: 080-42821618