Roland & Associates

Semiconductor Jobs opportunity (STA/DFT/PD/Layout/Verification Engineer/ASIC Design)

Greetings from Roland & Associates,

We have an excellent opportunity for Semiconductor Professionals for the following position.

1)  Physical Design Engineer
Role: Physical Design Engineer
Experience: 2 to 12 Years
Location: Bangalore/Hyderabad/Noida
Qualification: B.E/B.Tech/ME/M.Tech

Job description:-

Strong background of ASIC Physical Design
Floor Plan, Place & Route, Timing Analysis, Synthesis, Clock Tree Synthesis
Expertise in Scripting Languages like Perl & TCL
Verification Engineers (Specman/System Verilog)

2) Verification Engineer

Verification using System verilog/Specman/Systemc/Vera/SOC
Methodology : OVM, VMM,UVM,eRM
Expert in System verilog/Specman
Good in flow methodology with OVM/VMM/UVM/eRM

Experience level : 3-11 Years
Location : Bangalore/Hyderabad
Requirement Details:-

Proficiency in ASIC Verification.
Should have worked on SOC verification on at least one project with constrained random methodology (eRM/VMM/OVM).
Must be expert in Systemverilog/e/Vera/Specman/Systemc/C++/HVL

3) DFT Engineers:-

3 to 10 yrs of Experience in DFT area with both scan and mbist experience.
On the scan front, experience should include scan insertion and verification On the MBIST front, experience in memory BIST insertion and verification (include ModelSim or VCS simulator).
Design for testability: MBIST, PBIST, LBIST, MEBIST, ATPG,Tetramax.
Job Location: Bangalore

4)  STA/ASIC Synthesis Engineer

Role: STA/ASIC Synthesis Engineer
Experience: 2 to 10 Years
Location: Bangalore
Qualification: B.E/B.Tech/ME/M.Tech

Job description:-
-Experience on STA
-Should have worked on Synthesis using RTL complier
-Should have worked on STA using Gold Time
-Should be good at Flow and methodology.
-Knowledge of TCL is an added advantage
-Networking domain Knowledge is an added advantage
-Working knowledge of DDR is an added advantage .

5) IO Layout

Job description :
Role :Analog Layout or I/O Layout Engineer
Experience: 1 to 7 Years
Location : Bangalore
Qualification : Diploma/B.E/B.Tech/M.Tech

Required Skills :-

Very Good CMOS fundamental.
Sound knowledge of IO blocks like Design of the Transmitter /Receiver Blocks, Level Shifters.
Exposure to DDR IOs, XTAL IOs an added advantage.
Good Knowledge about IO Layout, should have work experience on 45nm (Below 45nm is highly preferable)
Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design.
Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS.

Professionals interested in exploring this opportunity, Can revert with your updated resume on saku@roljobs.com