Openings for RTL Design Engineer @ Chennai

Requirements:

Exp : 5-16 Years

Role: RTL Design Engineer

Location : Chennai

Experience in ASIC/ FPGA Design
USB 2.0 / 3.0 (Mandatory ; USB version should not be less than 2.0)
ASIC or FPGA Design (Mandatory)
RTL Coding using Verilog / VHDL
Microarchitecture Definition
DDR/AMBA/AHB/APB/AXI / PCIe
MOST (Optional)
Microlevel Architecture
Domain Expertise needed: USB (2.0, 3.0), AHB
Domain Optional : PCI Express, DDR2, AHB, Ethernet 802.3.x, WLAN, PCI

Candidates interested in exploring this opportunity, can mail your resume at phida@roljobs.com