US Based Semiconductor MNC Hiring for Memory Layout Engineer @ Bangalore mail me to lijith@roljobs.com

We have opening with one of our Client for Layout Engineer.

Location: Bangalore
Experience: 2 to 8 years

Position : Memory Layout Engineer

Candidate must have experience in layout design of memory leaf cells and at top level of memories
He/She should have worked on 65nm / 45nm / 28nm process technologies and have understanding of issues like WPE, LOD effects.
He/She must have good understanding of physical verification checks – DRC, LVS, ERC and reliability checks – IR and EM.
He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
He/She must have good understanding of Basics of CMOS circuits.
Preferable candidate to have Skill and perl scripting experience to develop layout and schematic tiler.

Professionals Interested in exploring the opportunity can revert to lijith@roljobs.com

Thanks & Regards,
Lijith V V
Roland & Associates -Leaders in Social Media Recruitment.