Hiring Memory Layout Engineer - Leading US based MNC in Semiconductor Domain @ Bangalore

Hi

We have an opening with one of our client for Memory Layout Engineers.

Responsibilities:

Candidate is expected to contribute individually by working hands-on layout design of SRAM/ROM/CAM/Custom memories and physical verification of memories.

He/She is expected to mentor/lead team of memory layout designer depending on requirement of project.

Candidate is required to interact and work with customer projects at their work place.

Candidate should have good communication skills, both verbal and oral. He/She should be a good team player.

Requirements:

Candidate must have experience in layout design of memory leaf cells and at top level of memories

He/She should have worked on 65nm/45nm/28nm process technologies and have understanding of issues like WPE, LOD effects

He/She must have good understanding of physical verification checks – DRC, LVS, ERC and reliability checks – IR and EM

He/She must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks

He/She must have good understanding of Basics of CMOS circuits

Preferable candidate to have Skill and perl scripting experience to develop layout and schematic tiler

Professionals interested in exploring this opportunity kindly forward their resume to prejith@roljobs.com