Job profile:
Responsibilities:
Execution of P&R, power/clock analysis, signal integrity avoidance/fixing, timing closure, noise analysis & DRC/LVS.
Perform custom layout functions to meet mixed signal layout and routing requirements
Define floorplan, including power busing, pin and pad placement, placement of blocks & macros
Physical chip integration and liaise with bond and frame order personnel
Document and update flow, work. Conduct reviews, and maintain required checklists
Work well as part of a team both locally, and also with remote or multi-site teams.
Mandatory Skills
Expertise in P & R, Physical Synthesis, CTS, floorplanning, Routing
Knowledge of low-power flow
Ability to perform layout vs. schematic (LVS) and design rule checks using the Calibre verification tools or similar
Experience in successful chip tapeouts
Experience with multiple industry level toolsets such as SOC encounter, Magma Talus and Synopsis ICC
Email your CV to saku@roljobs.com
Regards
Saku
Responsibilities:
Execution of P&R, power/clock analysis, signal integrity avoidance/fixing, timing closure, noise analysis & DRC/LVS.
Perform custom layout functions to meet mixed signal layout and routing requirements
Define floorplan, including power busing, pin and pad placement, placement of blocks & macros
Physical chip integration and liaise with bond and frame order personnel
Document and update flow, work. Conduct reviews, and maintain required checklists
Work well as part of a team both locally, and also with remote or multi-site teams.
Mandatory Skills
Expertise in P & R, Physical Synthesis, CTS, floorplanning, Routing
Knowledge of low-power flow
Ability to perform layout vs. schematic (LVS) and design rule checks using the Calibre verification tools or similar
Experience in successful chip tapeouts
Experience with multiple industry level toolsets such as SOC encounter, Magma Talus and Synopsis ICC
Email your CV to saku@roljobs.com
Regards
Saku
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