Saturday, August 11, 2012

:

Position : Physical design
Experience : 3- 9 years
Location : Bangalore
Qualification : B.E. / B.Tech / M.E. / M.Tech
 
 
·Should be capable of handling block of 1M plus place able instances
·Hands on experience in complete Netlist to GDS implementation on high frequency design
·Hands-On expertise in flip-chip designs.

Tools:
Magma Talus , ICC , SOCe, Apache , PrimeTimeSI, Calibre, Hercules.
·Successful implementation of multimillion gate SoC designs in 65nm,45nm,28nm technologies
·Work on all aspects of physical design including synthesis, IO ring creation, Bump placement , floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tape out.
 
Professionals interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume 

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